Influence of Dynamic Charge Compensation on Voltage
The grading capacitor is a conventional method to guarantee the uniform voltage distribution (VD) of double-break vacuum circuit breakers (VCBs). However, the main shield voltage
Mitigation of harmonics and unbalanced source voltage condition
The proposed compensation technique is based on the schematic as shown in Figure 9 in which compensation is provided through a compensating transformer which is
Dynamic compensation control strategy of DC bus
The voltage equation of a bus capacitor in Figure 1 can be written as: If the buck converter adopts single-voltage closed-loop control, the dynamic compensation of voltage can be achieved by adding only Q p,i. If the
Enhanced active feedback technique with dynamic compensation
by compensation capacitor C t1 and compensation resistor R t1. The pole and zero symbols marked '''' 0'''' represent the poles and zeros generated under heavy loads; otherwise, they refer
Statcom,Current Sampling And Voltage Sampling
Statcom, Current sampling and voltage sampling . Current and Voltage Sampling in STATCOM. Static Synchronous Compensator (STATCOM) is a device used for
Bootstrapped switch with improved linearity based on a negative voltage
The bootstrap capacitor C1 charges the sampling switch M8; thus, the gate–source voltage of the sampling switch is fixed near VDD. In this state, the output voltage follows the input signal.
Dynamic dc voltage regulation of split-capacitor DSTATCOM for
A distribution static compensator (DSTATCOM) is used for power quality improvement in the distribution system. a simple dynamic dc voltage regulation is proposed
4-5 A Dynamic Real-Time Capacitor Compensated Inductive
A Dynamic Real-time Capacitor Compensated Inductive Coupling Transceiver, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea E-mail: [email protected] Abstract A
Damping of Flying Capacitor Dynamics in Multi-Level Boost DC
This paper presents a novel modeling approach for flying capacitor dynamics in boost-type multi-level converters (FCML-boosts) controlled by Phase Shift Pulse Width
Dynamic Reactive Power Compensation
The fact that ''reactions'' are possible with power semiconductors within a network cycle increases the application area of a dynamic reactive power compensation system to include also voltage
A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling
A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision. Authors: Hongrui
A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in
However, the boosted voltage, which can be significantly reduced due to charge-sharing caused by parasitic capacitance at the gate of the sampling transistor MS, which is
Sample-and-hold circuit with dynamic switch leakage compensation
For sample-and-hold (S/H) circuits operating at low sampling rate and high temperature, the switch leakage current is one of the major error sources. A S/H circuit with dynamic switch
A dynamic‐range self‐compensation technique in a noise shaping
As Figure 1a shows, the connection of the bottom plates of least significant bit (LSB) capacitors is the same as the digital output (D OUT) of LSBs of the previous cycle (n − 1)
Switched-Capacitor Dynamic-Element-Matching Amplifier
In this paper an optimization on recently designed switched-capacitor dynamic- element- matching amplifier is presented. The main problem of this circuit is switch-charge injection.
Dynamic voltage restore based on switched-capacitor multilevel
The voltage harmonics and voltage unbalance, as well as voltage drop due to the electrical faults, can damage the sensitive loads. Various voltage compensators, such as the
Sample-and-hold circuit with dynamic switch leakage
A dynamic leakage current compensation technique is proposed for the S/H circuit. The new S/H circuit is capable of compensating the switch leakage currents regardless of whether the leakage is from the PMOS or the
An 88 dB SNDR Second-order CIFF Delta-sigma Modulator with
2 天之前· Unlike flash ADCs, SAR ADCs typically use a capacitor-based digital-to-analog converter (CDAC) for sampling the analog input voltage and generating the reference voltage,
A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with
A compensation structure is proposed to alleviate the sampling nonlinearity due to the charge injection from sampling switch, while the nonlinearity caused by the MIM capacitor''s
Capacitor Rating Selection for Voltage Sag Compensation in
bibliography on the capacitor element in the Dynamic Voltage Restorer (DVR). Various rating and sizing concerning the capacitor in the DVR power circuit problem have been highlighted.
Enhanced active feedback technique with dynamic compensation
capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and over-shoot are 59 and
Dynamic Offset Compensation 2 Techniques Dynamic
The output of G1 has to switch between the output voltage and the voltage VC over the compensation capacitor C 1. This voltage step itself can cause settling problems, which cause
Series and parallel resonance active damping of three-phase
of three-phase buck-type dynamic capacitor for reactive compensation and harmonic suppression ISSN 1755-4535 Received on 19th January 2020 Revised 24th March 2020 Accepted on 7th
A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling
Benefiting from the HV CMOS option offered by the used process, the wide-range input signal can be directly sampled on a part of the sampling capacitor during the sampling
Power quality improvement using ultra capacitor based dynamic voltage
The proposed scheme successfully reduced percentage total harmonics distortion and voltage sag using dynamic voltage restorer with sliding mode controller at
Transient response optimisation for peak current mode buck
By this way, an optimal gain for the transient output voltage is obtained and the optimaltransient response without overshoot and oscillation relative to V ref is validated by the circuit
Dynamic Capacitor (D-CAP): An Integrated Approach to Reactive
2518 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 6, NOVEMBER/DECEMBER 2010 Dynamic Capacitor (D-CAP): An Integrated Approach to
A Linearity Bootstrapped Switch with Dynamic Bulk Biasing
sampling mode. Our dynamic substrate voltage compensation circuit can connect the bulk terminal to the source of the transistor while in sampling mode, like [4], without decreasing the
Dynamic Capacitor (D-CAP): An Integrated Approach to
DC side capacitor voltage at sudden change of load is affected by the algorithm as well. This paper proposes a new algorithm for harmonic detection and compensation based on
Capacitor Voltage Feedback Active Damping With Reduced
A distortion-acceptable univariate feedback voltage dual-loop active damping control topology with much reduced computational delay is proposed, which is based on an
Damping of Flying Capacitor Dynamics in Multi-Level Boost DC
In this section, we address the flying capacitor voltage dynamics under PSPWM, deriving a newly conceived state space dynamic model. The main purpose of the
Sample-and-hold circuit with dynamic switch leakage compensation
This problem can be alleviated using higher sampling speed, or increasing the capacitance of the hold capacitor. A sample/hold circuit with dynamic switch leakage
A Simple and Efficient Charge Injection Error Compensation
800mV peak-to-peak amplitude at 50MHz sampling rate with a 1.8V supply voltage. Keywords: Analog switch; sample and hold; channel charge injection; clock feed
Design of Dynamic
simple method in which capacitors of the capacitor bank are placed in or out of the power network through switching the circuit breakers, relays that are slow response, and require
(PDF) Digital Constant On-Time V 2 Control With Hybrid Capacitor
Digital Constant On-Time V 2 Control With Hybrid Capacitor Current Ramp Compensation. estimator does not require high sampling rate, and avoids the current ramp
6 FAQs about [Capacitor dynamic compensation sampling voltage]
What does V mean on a sampling capacitor?
During the holding period, the voltage change, Δ V, on the sampling capacitor Cs caused by the leakage current Ileakage from the MOS sampling switch is given as Δ V = Ileakage / (2 FsCs ), where Fs is the sampling rate of the ADC. The least-significant-bit (LSB) of the N -bit ADC is defined as LSB = Vref /2 N in which Vref is the reference voltage.
What is a dynamic switch leakage compensation circuit?
A S/H circuit with dynamic switch leakage compensation is presented. The proposed leakage current compensation circuit generates switch leakage replicas that track the actual leakages in the sampling switches. A bidirectional current steering circuit allows the switch leakage to be dynamically compensated with the leakage replicas.
Can a sampling capacitor droop?
The switch is not ideal, since it has a leakage path that can cause either a droop or a rise of the voltage held on the sampling capacitor, depending on the direction of the leakage. This is especially severe under harsh operating conditions, such as in the oil and gas exploration industry, where the operating temperature can be above 200°C.
What is a dynamic leakage current compensation technique?
A dynamic leakage current compensation technique is proposed for the S/H circuit. The new S/H circuit is capable of compensating the switch leakage currents regardless of whether the leakage is from the PMOS or the NMOS switch or both, and has a very small area penalty of only 0.01 mm 2 in the chosen technology.
How to reduce sampling nonlinearity in MIM capacitors?
A compensation structure is proposed to alleviate the sampling nonlinearity due to the charge injection from sampling switch, while the nonlinearity caused by the MIM capacitor's voltage coefficients is cancelled digitally with the assistance of pseudo-random signal injection.
What causes capacitor mismatch & sampling errors in Digital Domain?
The capacitor mismatch and sampling errors due to the capacitor's voltage coefficients are calibrated in digital domain.
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